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fault protection and detection, 10 ? r on , 4 - channel multiplexer data sheet adg5404f rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2016 analog devices, inc. all rights reserved. technical support www.analog.com features overvoltage p rotection up to ? 55 v and +55 v power - off protection up to ?55 v and +55 v overvoltage detection on source pins interrupt flags indicate fault status low on resistance: 10 (typical) on - resistance flatness of 0.5 (maximum) 4 kv h uman b ody m odel (hbm) esd rating latch - up immune under any circumstance known state without digital input s present v ss to v dd analog signal range 5 v to 22 v dual supply operation 8 v to 44 v single - supply operation fu lly specified at 15 v, 20 v, 12 v, and 36 v applications analog input/o utput mod u les process control /d istributed c ontrol s ystems data acquisition instrumentation avionics automatic test equipment communication systems relay replacement functional block dia gram figure 1. general description the adg5404f is an analog multiplexer composed of four single channels with fault protected inputs. the adg5404f switches one of the four inputs to a common drain, d, as determined by the 2 - bit binary address lines ( a0 and a1 ) . an enable digital input, en, is used to disable all the switches. each channel conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. the digital inputs are compatible with 3 v logic inputs over the full operating supply range. when no power supplies are pres ent, the switch remains in the off condition, and the channel inputs are high impedance. under normal operating conditions, if the analog input signal levels on any sx pin exceed v dd or v ss by a threshold voltage, v t , the channel turns off and that sx pin becomes high impedance. if the channel is on, the drain pin react s according to the drain response (dr) input pin . if the dr pin is left floating or pulled high, the drain remain s high impedance and float s. if the dr pin is pulled low, the drain pull s to the exceeded rail . input signal levels up to +55 v or ?55 v relative to ground are blocked, in both the powered and unpowered condition s. the low on resistance of the adg5404f , combined wi th on - resistance flatness over a significant portion of the signal range , make s it an ideal solution for data acquisition and gain switching applications where excellent linearity and low distortion are critical. note that, throughout this data sheet, the dual function pin names are referenced only by the relevant function where applicable. see the pin configuration s and function descriptions for full pin names and function descriptions. product highlights 1. source pins are protected against voltages greater than the supply rails, up to ? 55 v and +55 v. 2. source pins are protected against voltages bet ween ? 55 v and +55 v in an unpowered state. 3. ove rvoltage detection with di gital output indicates operating state of switches. 4. tre nch isolation guards against latch - up. 5. optimi z ed for low on resistance and on - resistance flatness . 6. the adg5404f operates from a dual supply of 5 v up to 2 2 v , or a single power supply of 8 v up to 44 v . s1 s2 d s3 s4 adg5404f sf ff fault detection + switch driver a0/f0 a1/f1 en dr 12856-001
adg5404f data sheet rev. b | page 2 of 30 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual sup ply ....................................................................... 3 20 v dual supply ....................................................................... 5 12 v single supply ........................................................................ 7 36 v single supply ........................................................................ 9 continuous current ................................................................... 11 absolute maximum ratings .......................................................... 12 esd caution ................................................................................ 12 pin configurations and function descriptions ......................... 13 typical performance characteristics ........................................... 15 test circuits ..................................................................................... 20 terminology .................................................................................... 24 theory of operation ...................................................................... 26 switch a rchitecture .................................................................... 26 fault protection .......................................................................... 27 applications information .............................................................. 28 power supply rails ..................................................................... 28 power supp ly sequencing protection ...................................... 28 signal range ................................................................................ 28 low impedance channel protection ....................................... 28 power supply recommendations ............................................. 28 high voltage surge suppression .............................................. 28 intelligent fault detection ........................................................ 28 large voltage, high frequency signals ................................... 29 outline dimensions ....................................................................... 30 ordering g uide .......................................................................... 30 revision history 1 /1 6 rev. a to rev. b changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 3 ............................................................................ 7 changes to table 4 ............................................................................ 9 4/15 rev. 0 to rev. a added lfcsp package ....................................................... universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 7 changes to table 4 ............................................................................ 9 changes to table 5 .......................................................................... 11 changes to table 6 .......................................................................... 12 added figure 3 ; renumbered sequentially ................................ 13 changes to table 7 .......................................................................... 13 changes to figure 46 and figure 47............................................. 23 changes to switch architecture section ..................................... 26 changes to overv oltage interrupt flag section ......................... 27 added power supply recommendations section, figure 52, and table 10 ; renumbered sequentially ..................................... 28 add ed figure 54 .............................................................................. 30 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 12/1 4 revision 0 : initial version
data sheet adg5404f rev. b | page 3 of 30 specifications 15 v dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, c decoupling = 0.1 f, unless otherwise noted. table 1 . parameter +25c ? 40c to +85c ? 40c to +125c unit test conditions/comments analog switch v dd = 13.5 v, v ss = ?13.5 v, see figure 31 analog signal range v dd to v ss v on resistance, r on 10 typ voltage on the sx pins ( v s ) = 10 v, i s = ?10 ma 11.2 14 16.5 max 9.5 typ v s = 9 v, i s = ?10 ma 10.7 13.5 16 max on- resistance match between channels, ?r on 0.65 typ v s = 10 v, i s = ?10 ma 0.9 1.05 1.2 max 0.65 typ v s = 9 v, i s = ?10 ma 0.9 1.05 1.2 max on - resistance flatness, r flat(on) 0.6 typ v s = 10 v, i s = ?10 ma 0.9 1.1 1.1 max 0.1 typ v s = 9 v, i s = ?10 ma 0.4 0.5 0.5 max threshold voltage, v t 0.7 v typ see figure 27 leakage currents v dd = 16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.1 na typ v s = 10 v, voltage on the d pin (v d )= ? ?
adg5404f data sheet rev. b | page 4 of 30 parameter +25c ? 40c to +85c ? 40c to +125c unit test conditions/comments dynamic characteristics 1 transition time, t transi tion 400 ns typ r l = 300 , c l = 35 pf 540 555 570 ns max v s = 10 v, see figure 47 t on (en) 430 ns typ r l = 300 , c l = 35 pf 535 555 575 ns max v s = 10 v, see figure 46 t off (en) 180 ns typ r l = 300 , c l = 35 pf 225 230 235 ns max v s = 10 v, see figure 46 break - before - make time delay, t d 320 ns typ r l = 300 , c l = 35 pf 185 ns min v s = 10 v, see figure 45 overvoltage response time, t response 600 ns typ r l = 1 k, c l = 2 pf, see figure 40 775 820 840 ns max overvoltage recovery time, t recovery 700 ns typ r l = 1 k, c l = 2 pf, see figure 41 1000 1050 1100 ns max interrupt flag response time, t digresp 85 115 ns typ c l = 12 pf, see figure 42 interrupt flag recovery time, t digrec 60 85 s typ c l = 12 pf, see figure 43 600 ns typ c l = 12 pf, r pullup = 1 k, see figure 44 charge injection, q inj 680 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 48 off isolation ? 72 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 channel to channel cross talk ? 72 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 35 total harmonic distortion plus noise , thd + n 0.001 % typ r l = 10 k, v s = 15 v p - p, f = 20 hz to 20 khz, see figure 39 ? 3 db bandwidth 108 mhz typ r l = 50 , c l = 5 pf, see figure 38 insertion loss ? 0.9 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 source capacitance ( c s ), off 11 pf typ v s = 0 v, f = 1 mhz drain capacitance ( c d ), off 51 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 63 pf typ v s = 0 v, f = 1 mhz power requirements v dd = 16.5 v, v ss = ?16.5 v, gnd = 0 v, d igital inputs = 0 v, 5 v, or v dd normal mode i dd 0.9 ma typ 1.2 1.3 ma max i gnd 0.4 ma typ 0.55 0.6 ma max i ss 0.5 ma typ 0.65 0.7 ma max fault mode v s = 55 v i dd 1.2 ma typ 1.6 1.8 ma max i gnd 0.8 ma typ 1.0 1.1 ma max i ss 0.5 ma typ digital inputs = 5 v 1.0 1.8 ma max v s = 55 v, v d = 0 v v dd /v ss 5 v min gnd = 0 v 22 v max gnd = 0 v 1 guaranteed by design. n ot subject to production test.
data sheet adg5404f rev. b | page 5 of 30 20 v dual supply v dd = 20 v 10%, v ss = ? 20 v 10%, gnd = 0 v, c decoupling = 0.1 f, unless otherwise noted. table 2 . parameter + 25c ? 40c to +85c ? 40c to +125c unit test conditions/comments analog switch v dd = 18 v, v ss = ?18 v, see figure 31 analog signal range v dd to v ss v on resistance, r on 10 typ v s = 15 v, i s = ?10 ma 11.5 14.5 16.5 max 9.5 typ v s = 13.5 v, i s = ?10 ma 11 14 16.5 max on- resistance match between channels, ?r on 0.65 typ v s = 15 v, i s = ?10 ma 0.9 1.05 1.2 max 0.65 typ v s = 13.5 v, i s = ?10 ma 0.9 1.05 1.2 max on - resistance flatness, r flat(on) 1 .0 typ v s = 15 v, i s = ?10 ma 1.4 1.5 1.5 max 0.1 typ v s = 13.5 v, i s = ?10 ma 0.4 0.5 0.5 max threshold voltage, v t 0.7 v typ see figure 27 leakage currents v dd = 22 v, v ss = ?22 v source off leakage, i s (off ) 0.1 na typ v s = 15 v, v d = 15 v, see figure 32 1.5 5.0 21 na max drain off leakage, i d (off ) 0.3 na typ v s = 15 v, v d = 15 v, see figure 32 1.5 16.0 66 na max channel on leakage, i d (on), i s (on) 0.3 na typ v s = v d = 15 v, see figure 33 1.5 14.0 56 na max fau lt source leakage current, i s with overvoltage 85 a typ v dd = + 22 v, v ss = ?22 v, gnd = 0 v, v s = 55 v , see figure 36 power supplies grounded or floating 44 a typ v dd = 0 v or floating, v ss = 0 v or floating, gnd = 0 v, inx = 0 v or floating, ax = 0 v or floating, v s = 55 v, see figure 37 drain leakage current, i d dr = float ing or >2 v with overvoltage 400 na typ v dd = +22 v, v ss = ?22 v, gnd = 0 v, v s = 55 v , see figure 36 1.5 1.5 1.5 a max power supplies grounded 10 na typ v dd = 0 v, v ss = 0 v, gnd = 0 v, v s = 55 v, en = 0 v, see figure 37 30 50 100 na max power supplies floating 10 10 10 a typ v dd = floating, v ss = floating, gnd = 0 v, v s = 55 v, en = 0 v, see figure 37 digital inputs input voltage high, v inh 2.0 v min input voltage low, v inl 0.8 v max input current, i inl or i inh 0.7 a typ v in = v gnd or v dd 1.2 a max digital input capacitance, c in 6 .0 pf typ output voltage high, v oh 2.0 v min output voltage low, v ol 0.8 v max
adg5404f data sheet rev. b | page 6 of 30 parameter + 25c ? 40c to +85c ? 40c to +125c unit test conditions/comments dynamic characteristics 1 transi tion time, t transi tion 405 ns typ r l = 300 , c l = 35 pf 540 555 570 ns max v s = 10 v, see figure 47 t on (en) 430 ns typ r l = 300 , c l = 35 pf 535 560 585 ns max v s = 10 v, see figure 46 t off (en) 170 ns typ r l = 300 , c l = 35 pf 205 210 215 ns max v s = 10 v, see figure 46 break - before - make time delay, t d 330 ns typ r l = 300 , c l = 35 pf 200 ns min v s = 10 v, see figure 45 overvoltage response time, t response 480 ns typ r l = 1 k, c l = 2 pf, see figure 40 640 680 700 ns max overvoltage recovery time, t recovery 800 ns typ r l = 1 k, c l = 2 pf, see figure 41 1150 1250 1500 ns max interrupt flag response time, t digresp 85 115 ns typ c l = 12 pf, see figure 42 interrupt flag recovery time, t digrec 60 85 s typ c l = 12 pf, see figure 43 600 ns typ c l = 12 pf, r pullup = 1 k, see figure 44 charge injection, q inj 695 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 48 off isolation ? 73 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 channel to channel crosstalk ? 73 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 35 total ha rmonic distortion plus noise , thd + n 0.001 % typ r l = 10 k, v s = 20 v p - p, f = 20 hz to 20 khz, see figure 39 ? 3 db bandwidth 110 mhz typ r l = 50 , c l = 5 pf, see figure 38 insertion loss ? 0.9 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 c s (off ) 11 pf typ v s = 0 v, f = 1 mhz c d (off ) 47 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 61 pf typ v s = 0 v, f = 1 mhz power requirements v dd = 22 v, v ss = ?22 v, digital inputs = 0 v, 5 v, or v dd normal mode i dd 0.9 ma typ 1.2 1.3 ma max i gnd 0.4 ma typ 0.55 0.6 ma max i ss 0.5 ma typ 0.65 0.7 ma max fault mode v s = 55 v i dd 1.2 ma typ 1.6 1.8 ma max i gnd 0.8 ma typ 1.0 1.1 ma max i ss 0.5 ma typ digital inputs = 5 v 1.0 1.8 ma max v s = 55 v, v d = 0 v v dd /v ss 5 v min gnd = 0 v 22 v max gnd = 0 v 1 guaranteed by design. n ot subject to production test.
data sheet adg5404f rev. b | page 7 of 30 12 v single supply v dd = 12 v 10%, v ss = 0 v, g n d = 0 v, c decoupling = 0.1 f, unless otherwise noted. table 3 . parameter + 25c ? 40 c to +85c ? 40c to +125c unit test conditions/comments analog switch v dd = 10.8 v, v ss = 0 v, see figure 31 analog signal range 0 to v dd v on resistance, r on 22 typ v s = 0 v to 10 v, i s = ?10 ma 24.5 31 37 max 10 typ v s = 3.5 v to 8.5 v, i s = ?10 ma 11.2 14 16.5 max on- resistance match between channels, ?r on 0.65 typ v s = 0 v to 10 v, i s = ?10 ma 1.1 1.2 1.3 max 0.65 typ v s = 3.5 v to 8.5 v, i s = ?10 ma 0.9 1.05 1.2 max on - resistance flatness, r flat(on) 12.5 typ v s = 0 v to 10 v, i s = ?10 ma 14.5 19 23 max 0.6 typ v s = 3.5 v to 8.5 v, i s = ?10 ma 0.9 1.1 1.3 max threshold voltage, v t 0.7 v typ see figure 27 leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.1 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 32 1.5 5.0 21 na max drain off leakage, i d (off ) 0.3 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 32 1.5 16.0 66 na max channel on leakage, i d (on), i s (on) 0.3 na typ v s = v d = 1 v/10 v, see figure 33 1.5 14.0 56 na max fau lt source leakage current, i s with overvoltage 73 a typ v dd = 13.2 v, v ss = 0 v, gnd = 0 v, v s = 55 v, see figure 36 power supplies grounded or floating 44 a typ v dd = 0 v or floating, v ss = 0 v or floating, gnd = 0 v, en = 0 v or floating, v s = 55 v, see figure 37 drain leakage current, i d dr = float ing or >2 v with overvoltage 6 na typ v dd = 13.2 v, v ss = 0 v, gnd = 0 v, ax = 0 v or floating , v s = 55 v , see figure 36 15 35 80 na max power supplies grounded 10 na typ v dd = 0 v, v ss = 0 v, gnd = 0 v, v s = 55 v, en = 0 v, see figure 37 30 50 100 na max power supplies floating 10 10 10 a typ v dd = floating, v ss = floating, gnd = 0 v, v s = 55 v, en = 0 v, see figure 37 digital inputs input voltage high, v inh 2.0 v min input voltage low, v inl 0.8 v max input current, i inl or i inh 0.7 a typ v in = v gnd or v dd 1.2 a max digital input capacitance, c in 6 .0 pf typ output voltage high, v oh 2.0 v min output voltage low, v ol 0.8 v max
adg5404f data sheet rev. b | page 8 of 30 parameter + 25c ? 40 c to +85c ? 40c to +125c unit test conditions/comments dynamic characteristics 1 transi tion time, t transi tion 400 ns typ r l = 300 , c l = 35 pf 545 560 570 ns max v s = 10 v, see figure 47 t on (en) 430 ns typ r l = 300 , c l = 35 pf 530 545 560 ns max v s = 8 v, see figure 46 t off (en) 205 ns typ r l = 300 , c l = 35 pf 255 265 270 ns max v s = 8 v, see figure 46 break - before - make time delay, t d 290 ns typ r l = 300 , c l = 35 pf 175 ns min v s = 8 v, see figure 45 overvoltage response time, t response 700 ns typ r l = 1 k, c l = 2 pf, see figure 40 875 940 975 ns max overvoltage recovery time, t recovery 630 ns typ r l = 1 k, c l = 2 pf, see figure 41 780 830 920 ns max interrupt flag response time, t digresp 85 115 ns typ c l = 12 pf, see figure 42 interrupt flag recovery time, t digrec 60 85 s typ c l = 12 pf, see figure 43 600 ns typ c l = 12 pf, r pullup = 1 k, see figure 44 charge injection, q inj 322 pc typ v s = 6 v, r s = 0 , c l = 1 nf, see figure 48 off isolation ? 68 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 channel to channel crosstalk ? 70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 35 total harmonic distortion plus noise , thd + n 0.007 % typ r l = 10 k, v s = 6 v p - p, f = 20 hz to 20 khz, see figure 39 ? 3 db bandwidth 90 mhz typ r l = 50 , c l = 5 pf, see figure 38 insertion loss ? 0.9 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 c s (off ) 14 pf typ v s = 6 v, f = 1 mhz c d (off ) 66 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 76 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v, v ss = 0 v, digital inputs = 0 v, 5 v, or v dd normal mode i dd 0.9 ma typ 1.2 1.3 ma max i gnd 0.4 ma typ 0.55 0.6 ma max i ss 0.5 ma typ 0.65 0.7 ma max fault mode v s = 55 v i dd 1.2 ma typ 1.6 1.8 ma max i gnd 0.8 ma typ 1.0 1.1 ma max i ss 0.5 ma typ digital inputs = 5 v 1.0 1.8 ma max v s = 55 v, v d = 0 v v d d 8 v min gnd = 0 v 44 v max gnd = 0 v 1 guaranteed by design. n ot subject to production test.
data sheet adg5404f rev. b | page 9 of 30 36 v single supply v dd = 36 v 10%, v ss = 0 v, g n d = 0 v, c decoupling = 0.1 f, unless otherwise noted. table 4 . parameter + 25c ? 40c to +85c ? 40c to +125c unit test conditions/comments analog switch v dd = 32.4 v, v ss = 0 v, see figure 31 analog signal range 0 to v dd v on resistance, r on 22 typ v s = 0 v to 30 v, i s = ?10 ma 24.5 31 37 max 10 typ v s = 4.5 v to 28 v, i s = ?10 ma 11 14 16.5 max on- resistance match between channels, ?r on 0.65 typ v s = 0 v to 30 v, i s = ?10 ma 1.1 1.2 1.3 max 0.65 typ v s = 4.5 v to 28 v, i s = ?10 ma 0.9 1.05 1.2 max on - resistance flatness, r flat(on) 12.5 typ v s = 0 v to 30 v, i s = ?10 ma 14.5 19 23 max 0.1 typ v s = 4.5 v to 28 v, i s = ?10 ma 0.4 0.5 0.5 max threshold voltage, v t 0.7 v typ see figure 27 leakage currents v dd =39.6 v, v ss = 0 v source off leakage, i s (off ) 0.1 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 32 1.5 5.0 21 na max drain off leakage, i d (off ) 0.3 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 32 1.5 16.0 66 na max channel on leakage, i d (on), i s (on) 0.3 na typ v s = v d = 1 v/30 v, see figure 33 1.5 14.0 56 na max fau lt source leakage current, i s with overvoltage 68 a typ v dd = 39.6 v, v ss = 0 v, gnd = 0 v, v s = +55 v, ?40 v , see figure 36 power supplies grounded or floating 44 a typ v dd = 0 v or floating, v ss = 0 v or floating, gnd = 0 v, a x = 0 v or floating, v s = +55 v, ?40 v, see figure 37 drain leakage current, i d dr = float ing or >2 v with overvoltage 6 na typ v dd = 39.6 v, v ss = 0 v, gnd = 0 v, v s = +55 v , ?40 v, see figure 36 15 35 80 na max power supplies grounded 10 na typ v dd = 0 v, v ss = 0 v, gnd = 0 v, v s = +55 v, ?40 v, en = 0 v, see figure 37 30 50 100 na max power supplies floating 10 10 10 a typ v dd = floating, v ss = floating, gnd = 0 v, v s = +55 v, ?40 v, en = 0 v, see figure 37 digital inputs input voltage high, v inh 2.0 v min input voltage low, v inl 0.8 v max input current, i inl or i inh 0.7 a typ v in = v gnd or v dd 1.2 a max digital input capacitance, c in 6 .0 pf typ output voltage high, v oh 2.0 v min output voltage low, v ol 0.8 v max
adg5404f data sheet rev. b | page 10 of 30 parameter + 25c ? 40c to +85c ? 40c to +125c unit test conditions/comments dynamic characteristics 1 transi tion time, t transi tion 400 ns typ r l = 300 , c l = 35 pf 540 555 570 ns max v s = 10 v, see figure 47 t on (en) 430 ns typ r l = 300 , c l = 35 pf 530 550 570 ns max v s = 18 v, see figure 46 t off (en) 175 ns typ r l = 300 , c l = 35 pf 210 215 220 ns max v s = 18 v, see figure 46 break - before - make time delay, t d 340 ns typ r l = 300 , c l = 35 pf 200 ns min v s = 18 v, see figure 45 overvoltage response time, t response 270 ns typ r l = 1 k, c l = 2 pf, see figure 40 360 375 385 ns max overvoltage recovery time, t recovery 1400 ns typ r l = 1 k, c l = 2 pf, see figure 41 1900 2100 2400 ns max interrupt flag response time, t digresp 85 115 ns typ c l = 1 2 pf, see figure 42 interrupt flag recovery time, t digrec 60 85 s typ c l = 12 pf, see figure 43 600 ns typ c l = 12 pf, r pullup = 1 k, see figure 44 charge injection, q inj 588 pc typ v s = 18 v, r s = 0 , c l = 1 nf, see figure 48 off isolation ? 72 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 channel to channel crosstalk ? 73 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 35 total harmonic distortion plus noise , thd + n 0.001 % typ r l = 10 k, v s = 18 v p - p, f = 20 hz to 20 khz, see figure 39 ? 3 db bandwidth 108 mhz typ r l = 50 , c l = 5 pf, see figure 38 insertion loss ? 0. 9 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 c s (off ) 11 pf typ v s = 18 v, f = 1 mhz c d (off ) 48 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 60 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v, v ss = 0 v, digital inputs = 0 v, 5 v, or v dd normal mode i dd 0.9 ma typ 1.2 1.3 ma max i gnd 0.4 ma typ 0.55 0.6 ma max i ss 0.5 ma typ 0.65 0.7 ma max fault mode v s = +55 v, ?40 v i dd 1.2 ma typ 1.6 1.8 ma max i gnd 0.8 ma typ 1.0 1.1 ma max i ss 0.5 ma typ digital inputs = 5 v 1.0 1.8 ma max v s = + 55 v, ? 40 v, v d = 0 v v dd 8 v min gnd = 0 v 44 v max gnd = 0 v 1 guaranteed by design. n ot subject to production test.
data sheet adg5404f rev. b | page 11 of 30 continuous current table 5 . parameter 25c 85c 125c unit test conditions/comments 14 - lead tssop ja = 112.6c/w 147 95 58 ma max v s = v ss + 4.5 v to v dd ? 4.5 v 115 77 50 ma max v s = v ss to v dd 16 - lead lfcsp ja = 30.4c/w 280 156 75 ma max v s = v ss + 4.5 v to v dd ? 4.5 v 220 130 70 ma max v s = v ss to v dd
adg5404f data sheet rev. b | page 12 of 30 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating v dd to v ss 48 v v dd to gnd ? 0.3 v to + 48 v v ss to gnd ? 48 v to +0.3 v sx to gnd ? 55 v to +55 v sx to v dd or v ss 80 v v s to v d 80 v d pin 1 to gnd v ss ? 0. 7 v to v dd + 0. 7 v or 30 ma, whichever occurs first digital inputs to gnd gnd ? 0. 7 v to 48 v or 30 ma, whichever occurs first peak current, sx or d pins 363 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, sx or d data 2 + 15% digital output gnd ? 0.7 v to 6 v or 30 ma, whichever occurs first d pin , overvoltage s tate, dr = gnd, load current 1 ma operating temperature range ? 40c to +125c storage temperature range ? 65c to +150c junction temperature 150c thermal impedance, ja 1 4 - lead tssop, thermal impedance (4 - layer board) 112.6c/w 16 - lead lfcsp, thermal impedance (4 - layer board) 30.4c/w reflow soldering peak temperature, pb - free as per jedec j - std -020 esd rating, human body model (hbm ) : ansi/esd stm5.1 - 2007 i nput /o utput (i/o) port to supplies 4 kv i/o port to i/o port 4 kv all other pins 4 kv 1 overvoltages at the d pin are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability . only one absolute maximum rating can be applied at any one time. esd caution
data sheet adg5404f rev. b | page 13 of 30 pin configuration s and function descrip tions figure 2 . tssop pin configuration figure 3 . lfcsp pin configuration table 7 . pin function descriptions pin no. mnemonic description tssop lfcsp 1 15 a0/f0 1 logic control input (a0). decoder for the sf pin (f0). 2 16 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, the ax logic control inputs determine the on switches. 3 1 v ss most negative power supply potential. 4 3 s1 overvoltage protected source terminal 1. this pin can be an input or an output. 5 4 s2 overvoltage protected source terminal 2. this pin can be an input or an output. 6 6 d drain terminal. this pin can be an input or an output. 7 5 dr drain response digital input. tying this pin to gnd enables the drain to pull to v dd or v ss during an overvoltage fault condition. the default condition of the drain is open circuit when the pin is left floating or if it is tied to v dd . 8 7 sf specific fault digital output. this pin has a high output when the device is in normal operation and a low output when a fault condition is detected on a specific pin, depending on the state of a0/f0 and a1/f1 (see table 9 ). 9 8 ff fault flag digital output. this pin has a high output when the device is in normal operation and a low output when a fault condition occurs on any of the sx inputs. 10 9 s4 overvol tage protected source terminal 4. this pin can be an input or an output. 11 10 s3 overvoltage protected source terminal 3. this pin can be an input or an output. 12 11 v dd most positive power supply potential. 13 12 gnd ground (0 v) reference. 14 14 a1/f1 1 logic control input (a1). decoder for the sf pin (f1). 2, 13 nic not internally connected n/a 2 17 ep the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 1 throughout the data sheet, dual function pin names are referenced by the relevan t function where applicable. 2 n/a means not applicable. 1 2 3 4 5 6 7 en v ss s1 dr d s2 a0/f0 14 13 12 1 1 10 9 8 gnd v dd s3 sf ff s4 a1/f1 adg5404f t o p view (not to scale) 12856-002 12856-103 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 notes 1. nic = not internal l y connected. 2. the exposed p ad is connected internal l y . for increased reliabilit y of the solder joints and maximum therma l ca p abilit y , it is recommended th a t the p ad be soldered t o the substr a te, v ss . v ss nic s1 s2 gnd nic a1/f1 a0/f0 en v dd s3 s4 dr d sf ff adg5404f t op view (not to scale)
adg5404f data sheet rev. b | page 14 of 30 table 8 . truth table en a1 a0 connected sx pin 0 x 1 x 1 all switches off 1 0 0 s1 1 0 1 s2 1 1 0 s3 1 1 1 s4 1 x means dont care. table 9 . fault diagnost ic o utput truth table switch in fault 1 state of specific fault pin (sf ) with decoder pins (f1, f0) state of the fault flag pin (ff) f1 = 0, f0 = 0 f1 = 0, f0 = 1 f1 = 1, f0 = 0 f1 = 1, f0 = 1 no switch in fault 1 1 1 1 1 s1 0 1 1 1 0 s2 1 0 1 1 0 s3 1 1 0 1 0 s4 1 1 1 0 0 1 more than one source input can be in fault at the same time.
data sheet adg5404f rev. b | page 15 of 30 typical performance characteristics figure 4. r on as a function of v s and v d , dual supply figure 5. r on as a function of v s and v d , 12 v single supply figure 6. r on as a function of v s and v d , 36 v single supply figure 7. r on as a function of v s and v d for different temperatures, 15 v dual supply figure 8. r on as a function of v s and v d for different temperatures, 20 v dual supply figure 9. r on as a function of v s and v d for different temperatures, 12 v single supply 25 20 15 10 5 0 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance (?) v s , v d (v) t a = 25c v dd = +22v v ss = ?22v v dd = +20v v ss = ?20v v dd = +18v v ss = ?18v v dd = +16.5v v ss = ?16.5v v dd = +15v v ss = ?15v v dd = +13.5v v ss = ?13.5v 12856-003 25 20 15 10 5 0 0 14 12 10 8 6 4 2 on resistance (?) v s , v d (v) t a = 25c v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 12856-004 25 20 15 10 5 0 0 40 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) t a = 25c v dd = 36v v ss = 0v v dd = 32.4v v ss = 0v v dd = 39.6v v ss = 0v 12856-005 40 30 20 35 25 15 10 5 0 ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 on resistance (?) v s , v d (v) v dd = +15v v ss = ?15v +125c +85c +25c ?40c 12856-006 40 30 20 35 25 15 10 5 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance (?) v s , v d (v) v dd = +20v v ss = ?20v +125c +85c +25c ?40c 12856-007 40 30 20 35 25 15 10 5 0 0 2 4 6 8 10 12 on resistance (?) v s , v d (v) v dd = 12v v ss = 0v +125c +85c +25c ?40c 12856-008
adg5404f data sheet rev. b | page 16 of 30 figure 10 . r on as a function of v s and v d for different temperatures, 36 v single supply figure 11 . leakage current vs. temperature, 15 v dual supply figure 12 . leakage current vs. temperature, 20 v dual supply figure 13 . leakage current vs. temperature, 12 v single supply figure 14 . leakage current vs. temperature, 36 v single supply figure 15 . overvoltage leakage current vs. temperature, 15 v dual supply 40 30 20 35 25 15 10 5 0 0 4 8 12 20 28 36 16 24 32 on resistance (?) v s , v d (v) v dd = 36v v ss = 0v +125c +85c +25c ?40c 12856-009 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 20 40 60 80 100 120 leakage current (na) temperature (c) i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i s , i d (on)++ i s , i d (on) ? ? v dd = +15v v ss = ?15v v bias = +10v, ?10v 12856-010 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 20 40 60 80 100 120 leakage current (na) temper a ture (c) i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i s , i d (on)++ i s , i d (on) ? ? v dd = +20v v ss = ?20v v bias = +15v, ?15v 12856-0 1 1 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 20 40 60 80 100 120 leakage current (na) temper a ture (c) 12856-012 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i s , i d (on)++ i s , i d (on) ? ? v dd = +12v v ss = 0v v bias = +1v, +10v ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 20 40 60 80 100 120 leakage current (na) temper a ture (c) 12856-013 i s (off) +? i d (off) +? i s (off) ?+ i d (off) ?+ i s , i d (on)++ i s , i d (on) ? ? v dd = +36v v ss = 0v v bias = +1v, +30v ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 20 40 60 80 100 120 ove r volt age leakage current (na) temper a ture (c) v dd = +15v v ss = ?15v v s = ?55v v s = +55v 12856-014
data sheet adg5404f rev. b | page 17 of 30 figure 16 . overvoltage leakage current vs. temperature, 20 v dual supply figure 17 . overvoltage leakage current vs. temperature, 12 v single supply figure 18 . overvoltage leakage current vs. temperature, 36 v single supply figure 19 . off isolation vs. frequency figure 20 . crosstalk vs. frequency figure 21 . charge injection vs. source voltage (v s ) , single supply 0 20 40 60 80 100 120 ove r volt age leakage current (na) temper a ture (c) 12856-015 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 v dd = +20v v ss = ?20v v s = ?55v v s = +55v ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 5 0 0 20 40 60 80 100 120 ove r volt age leakage current (na) temper a ture (c) v dd = 12v v ss = 0v v s = ?55v v s = +55v 12856-016 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 20 40 60 80 100 120 ove r volt age leakage current (na) temper a ture (c) v dd = 36v v ss = 0v v s = ?55v v s = +55v 12856-017 ?120 ?100 ?80 ?60 ?40 ?20 0 10k 100k 1m 10m 100m 1g 10g off isol a tion (db) frequenc y (hz) t a = 2 5c v dd = + 15 v v ss = ?15 v 12856-018 ?120 ?100 ?80 ?60 ?40 ?20 0 10k 100k 1m 10m 100m 1g 10g crosstalk (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 12856-019 ?200 ?100 0 100 200 300 400 500 600 700 800 0 5 10 15 20 25 30 35 40 charge injection (pc) v s (v) v dd = 12v, v ss = 0v v dd = 36v, v ss = 0v t a = 25c 12856-020
adg5404f data sheet rev. b | page 18 of 30 figure 22 . charge injection vs. source voltage (v s ), dual supply figure 23 . acpsrr vs. frequency figure 24 . thd + n vs. frequency figure 25 . bandwidth vs. frequency figure 26 . t transition vs. temperature figure 27 . threshold v oltage (v t ) vs. temperature ?200 0 200 400 600 800 1000 ?20 ?15 ?10 ?5 0 5 10 15 20 charge injection (pc) v s (v) v dd = 20v, v ss = ?20v v dd = 15v, v ss = ?15v t a = 25c 12856-021 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m 100m 1g acpsrr (db) frequenc y (hz) t a = 2 5c v dd = + 15 v v ss = ? 15 v w i t h d e c o up li ng c a p s 12856-022 0 0.005 0.010 0.015 0.020 0 5 10 15 20 thd + n (%) frequency (khz) r load = 10k? t a = 25c v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 36v, v ss = 0v, v s = 18v p-p v dd = 15v, v ss = ?15v, v s = 15v p-p v dd = 20v, v ss = ?20v, v s = 20v p-p 12856-023 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 10k 100k 1m 10m 100m bandwidth (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 12856-024 455 460 465 470 475 480 485 490 495 12856-025 ?40 ?20 0 20 40 60 80 100 120 t transition (ns) temper a ture (c) v dd = 12v, v ss = 0v v dd = 36v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v 0.9 0.8 0.7 0.6 0.5 0 120 100 80 60 40 20 ?20 ?40 threshold voltage, v t (v) temperature (c) 12856-026
data sheet adg5404f rev. b | page 19 of 30 figure 28 . drain o utput r esponse to p ositive o vervoltage figure 29 . drain o utput r esponse to n egative o vervoltage figure 30 . large s ignal voltage t racking vs. frequency ch1 5.00v ch3 5.00v ch2 5.00v m400ns a ch2 10.1v t ?10.00ns 2 t drain source v dd 12856-027 ch1 5.00v ch3 5.00v ch2 5.00v m400ns a ch2 ?14.7v 1 drain source v ss t ?10.00ns 12856-028 24 20 16 12 8 4 0 100 10 1 signal voltage (v p-p) frequency (mhz) distortionless operating region t a = 25c v dd = +10v v ss = ?10v 12856-029
adg5404f data sheet rev. b | page 20 of 30 test circuits figure 31 . on resistance figure 32 . off leakage figure 33 . channel on leakage figure 34 . off isolation figure 35 . channel to channel crosstalk figure 36 . switch overvoltage leakage figure 37 . switch unpowered leakage figure 38 . bandwidth i ds sx d v s v r on = v/i ds 12856-030 s1 d v s a a v d i s (o ff) i d (o ff) s4 a 12856-031 nc nc = no connect s2 v s v d s4 s1 (on) d 12856-032 a i d (o n) v out 50 network analyzer r l 50 ax v in sx d off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 12856-033 channel to channel crosstalk = 20 log v out gnd s1 d s2 network analyzer r l 50 r l 50 v s v dd v ss 0.1f v dd 0.1f v ss v s v out 12856-034 |v s | > | v dd | or | v ss | sx d a a i s i d r l 10k? 12856-035 v s v dd = v ss = gnd = 0v sx d a a i s i d r l 10k? 12856-036 v out 50 network analyzer r l 50 ax v in sx d insertion loss = 20 log v out with switch v out w i t h o u t sw i t c h v s v dd v ss 0.1f v dd 0.1f v ss gnd 12856-037
data sheet adg5404f rev. b | page 21 of 30 figure 39 . thd + n figure 40 . overvoltage response time, t response figure 41 . overvoltage recovery time, t recovery v out r s audio precision r l 10k ax v in sx d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 12856-038 v d adg5404f gnd s1 s2 to s4 d c l * 2pf 0.1f 0.1f v s v dd v ss v dd v ss v dd + 0.5v v dd ? 0.9v 0v 0v output (v d ) t response source voltage (v s ) r l 1k *includes track capacitance 12856-039 v d adg5404f gnd s1 s2 to s4 d c l * 2pf 0.1f 0.1f v s v dd v ss v dd v ss r l 1k *includes track capacitance v dd + 0.5v 1v 0v 0v output (v d ) t recovery source voltage (v s ) 12856-040
adg5404f data sheet rev. b | page 22 of 30 figure 42 . interrupt flag response time, t digresp figure 43 . interrupt flag recovery time, t digrec figure 44 . interrupt flag recovery time, t digrec , with a 1 k? pull - up resistor adg5404f gnd s1 ff d 0.1f 0.1f v s v dd v ss v dd v ss s2 to s4 *includes track capacitance c l * 12pf v dd + 0.5v 0v 0v output (v ff ) t digresp 0.1v out source voltage (v s ) 12856-041 adg5404f gnd s1 ff d 0.1f 0.1f v s v dd v ss v dd v ss s2 to s4 *includes track capacitance c l * 12pf v dd + 0.5v 0v 0v output (v ff ) t digrec 0.9v out source voltage (v s ) 12856-042 adg5404f gnd s1 ff d 0.1f 0.1f v s v dd v ss v dd v ss s2 to s4 *includes track capacitance c l * 12pf v dd + 0.5v 0v 5v 0v output (v ff ) t digrec 3v source voltage (v s ) r pullup 1k 5v output 12856-043
data sheet adg5404f rev. b | page 23 of 30 figure 45 . break - before - make time delay, t d figure 46 . enable delay, t on (en), t off (en) figure 47 . address to output switching times, t transition figure 48 . charge injection , q inj v dd v ss v dd v ss c l 35 p f r l 300 ? addr ess dr i ve (v in ) v out v out v in s1 d gnd 300? a 0 a 1 s4 s3 s2 v s en 2.4v 0 . 1 f 0 . 1 f t d 80 % 80 % 0v 3v 12856-044 e nab l e dr i ve (v i n ) s1 d g n d c l 35 p f r l 300 ? a 0 a 1 s4 s3 s2 en 0 . 1 f 0 . 1 f v in t off ( e n ) t on ( e n ) 50 % 50 % 90% 10% o u t p u t 0 v 3 v v out 0 v v dd v ss v dd v ss v s v out 12856-045 v dd v ss v dd v ss v in s1 d gnd c l 35 p f r l 300 ? v out v out 50 % 50 % 1 0 % 90 % addr ess dr i ve (v i n ) ) a0 a1 s4 s3 s2 v s en 2 . 4 v 0 v 3 v 0v t transition t transition 0.1f 0.1f 12856-046 inx v out adg5404f v in v out on v out off q inj = c l v out sx en d v dd v ss v dd v ss v s r s gnd c l 1nf 0.1f 0.1f 12856-047
adg5404f data sheet rev. b | page 24 of 30 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on the d pin and the sx pins, respectively. r on r on represents the ohmic resistance between the d pin and the sx pins. ? r on ? r on represents the difference between the r on of any two channels. r flat(on) r flat(on) is the flatness defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, whi ch is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with referenc e to ground. c in c in is the digital input capacitance. t on t on represents the delay between applying the digital control input and the output switching on (see figure 46). t off t off represents the delay between applying the digital control input and the output switching off (see figure 46). t d t d represents the off time measured between the 90% point of both switches when switching from one address state to another. t digresp t digresp is the time required for the ff pin to go low (0.3 v), measured with respect to the voltage on the source pin exceeding the supply voltage by 0.5 v. t digrec t digrec is the time required for the ff pin to return high, measured with respect to the voltage on the sx pin falling below the supply volta ge plus 0.5 v. t response t response represents the delay between the source voltage exceeding the supply voltage by 0.5 v and the drain voltage falling to 90% of the supply voltage . t recovery t recovery r epresents the delay between an overvoltage on the sx pin falling below the supply voltage plus 0.5 v and the drain voltage rising from 0 v to 10% of the supply voltage . off isolation off isolation is a measure of unwanted signal coupling through an off switch. charge injection charge injection is a measur e of the glitch impulse transferred from the digital input to the analog output during switching. channel to channel crosstalk channel to channel c rosstalk is a measure of unwanted signal coupled through from one channel to another as a result of parasiti c capacitance. ? 3 db bandwidth ? 3 db b andwidth is the frequency at which the output is attenuated by ? 3 db. on response on response is the frequency response of the on switch. insertion loss insertion loss is the loss due to the on resistance of the switch. total harmonic distortion plus noise (thd + n) thd + n is the ratio of the harmonic amplitude plus noise of the signal to the fundamental.
data sheet adg5404f rev. b | page 25 of 30 ac power supply rejection ratio (acpsrr) acpsrr is the ratio of the amplitude of signal on the output to the amplitude of the modulation. acpsrr is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch . the dc voltage on the device is modulated by a sine wave of 0.62 v p - p. v t v t is the v oltage threshold at which the overvoltage protection circuitry engag es (s ee figure 27).
adg5404f data sheet rev. b | page 26 of 30 theory of operation switch architecture each channel of the adg54 04f consists of a parallel pair of ndmos and pdmos transistors. this construction provides excellent performance across the signal range. the adg5404f channels operate as standard switches whe n input signals with a voltage between v ss and v dd are applied. for example, the on resistance is 10 ? typically , and opening or closing the switch is controlled using the appropriate control pin s. additional internal circuitry enables the switch to detect overvoltage inputs by comparing the voltage on the source pin with v dd and v ss . a signal is considered overvoltage if it exceeds the supply voltages by the voltage threshold, v t . the threshold voltage is typically 0.7 v, but can range from 0.8 v at ? 40c down to 0.6 v at +125c. see figure 27 to see the change in v t with operating temperature. the maximum voltage that can be applied to any s ource input is ? 55 v or + 55 v. when the device is powered using the single supply of 25 v or greater , the maximum signal level is reduced. it reduces from ?55 v at v dd = +25 v to ?40 v at v dd = +40 v to remain within the 80 v maximum rating. the c onstruction of the process allows the channel to withstand 80 v across the switch when it is opened. these overvoltage limits apply whether the power supplies are present or not. figure 49 . switch channel and control function when an overvoltage condition is det ected on a source pin (sx), the switch automatically opens and the source pin (sx) becomes high impedance and ensures that no current flows through the switch. if the dr pin is driven low, the drain p in, d, is pulled to the supply that was exceeded. for ex ample, if the source voltage exceeds v dd , the drain output pulls to v dd . the same is true for v ss . if the dr pin is allowed to float or is driven high, pin d also becomes open circuit. the voltage on pin d follows the voltage on the source pin, sx, until the switch turns off completely and the d rain voltage discharges through the load. the maximum voltage on the drain is limited by the internal esd diodes and the rate at which the output voltage discharges is dependent on the load at the pin. duri ng overvoltage conditions, the leakage current into and out of the source pins (sx) is limited to tens of microamperes. if the dr pin is allowed to float or is driven high, only nanoamperes of leakage are seen on the drain pin (d). if the dr pin is driven low, the drain pin (d) is pulled to the rail . the device that pulls the drain pin to the rail has an impedance of approximately 40 k?, so the dx pin current will be limited to about 1 ma during a shorted load condition. this internal impedance will also de termine the minimum external load resistance required to ensure the drain pin is pulled to the desired voltage level during a fault. when an overvoltage event occurs, the channels undisturbed by the overvoltage input continue to operate normally without a dditional crosstalk . esd performance the adg5404f has an esd (hbm) rating of 4 k v. the drain pin has esd protection diodes to the rails , and the voltage at this pin must not exceed supply voltage. the source p ins have specialized esd protection that allow the signal voltage to reach from ? 55 v to +55 v with a 22 v dual supply , and from ? 40 v to +55 v with a 40 v single supply. see figure 49 for the switch channel overview. trench isolation in the adg5404f , an insulating oxide layer (trench) is placed between the ndmos and the pdmos transistors of each switch. parasitic junctions, which occur betw een the transistors in junction isolated switches, are eliminated, and the result is a switch that is latch - up immune under all circumstance s. this device pass es a jesd78d latch - up test of 500 ma for 1 sec, the strictest test in the specification. figure 50 . trench isolation fault detector esd protection switch driver sx dx dr v dd v ss esd diode esd diode 12856-048 logic bock ndmos pdmos p- w e l l n - w e l l buried oxide layer handle wafer t r e n c h 12856-049
data sheet adg5404f rev. b | page 27 of 30 fault protection when the voltages at the source inputs exceed v dd or v ss by v t , the switc h turns off , or, if the device is unpowered, the switch remains off. the switch input remains high impedance regardless of the digital input state or the load resistance , and the output acts as a virtual open circuit. signal levels up to +55 v and ? 55 v ar e blocked in both the powered and unpowered condition s as long as the 80 v limitation between the source and supply pins is met. power - on protection the following three conditions must be satisfied for the switch to be in the on condition: ? v dd to v ss 8 v . ? input signal is between v ss ? v t and v dd + v t . ? the d igital logic control input, a x , is turned on . when the switch is turned on, the signal levels up to the supply rails are passed. the switch responds to an analog input that exceeds v dd or v ss by a threshold voltage, v t , by turning off. the absolute input voltage limits are ?55 v and +55 v, while maintaining an 80 v limit between the source pin and the supply rails. the switch remains off until the voltage at the source pin returns to between v dd and v ss . the fault response time (t response ) when powered by a 15 v dual supply is typically 600 ns , and the fault recovery time (t recovery ) is 700 ns. these vary with supply voltages and output load conditions. exceeding 55 v on any source input may damage the esd protection circuitry on the device. the maximum stress across the switch channel is 80 v . t herefore , the user must pay close attention to this limit when using the device with a 40 v single supply. in this case, the maximum undervoltage cond ition is ? 40 v to maintain the 80 v across the switch channel. for undervoltage and overvoltage conditions, consider the case where the device is set up as shown in figure 51. ? v dd /v ss = 22 v, s 4 = 2 2 v, and s4 is on . t herefore , d = 22 v ? s 1 and s2 have a ?55 v fault and s 3 has a + 55 v fault . ? the voltage between s 1 and d or between s2 and d = +22 v ? (?55 v) = +77 v . ? the voltage between s3 and d = 22 v? 55 v = ? 33 v . th ese calculations are all within the device specifications: a 55 v maximum fault on source inputs and a maximum of 80 v across the off switch channel. ff is low due to the fault condition on s1, s2 , a nd s3. sf is high because there is no f ault condition on s4 as decoded by f1 = 1, f0 = 1 . figure 51 . example fault condition setup power - off protection when no power supplies are present, the switch remains in the off condition, and the switch inputs are high impedance. this state ensures that no current flows and prevents damage to the switch or downstream circuitry. the switch output is a virtual open c ircuit. the switch remains off regardless of whether the v dd and v ss supplies are 0 v or floating. a gnd reference must always be present to ensure proper operation. signal levels of up to 55 v are blocked in the unpowered condition. digital input prote ction the adg5404f can tolerate unpowered digital input signals present on the device. when the device is unpowered, the switch is guaranteed to be in the off state, regardless of the state of the digital logic signals. the digital inputs are protected against positive faults up to 44 v. the digital inputs do not offer protection against negative overvoltages. esd protection diodes connected to gnd are present on the digital inputs. overvoltage interrupt flag the voltages on the source inputs of the adg5404f are continuously monitored , and the state of the switch is indicated by an active low digital output pin, ff. the voltage on th e ff pin indicates if any of the source input pins are experiencing a fault condition. the output of the ff pin is a nominal 3 v when all source pins are within normal operating range. if any source pin voltage exceeds the supply voltage by v t , the ff ou tput reduces to below 0.8 v. use t he specific fault digital output pin , sf , to decode which inputs are e xperiencing a fault condition. the sf pin reduces to below 0.8 v when a fault condition is detected on a specific pin, depending on the state o f f0 and f1 (see table 9 ) . the specific fault feature also works with the switches disabled (en pin low), which allows the user to cycle through and check the fault conditions without connecting the fault to the drai n output. +22v ?9 ?9 +55v 0v 3v 12856-050 s1 s2 d s3 s4 adg5404f sf ff fault detection + switch driver a0 a1 en dr v dd v ss gnd +22v ?22v 0v 5v
adg5404f data sheet rev. b | page 28 of 30 applications informa tion the overvoltage protected family of switches and multiplexers provide a robust solution f or instrumentation, industrial , aerospace, and other harsh environments where overvoltage signals can be present and the system must remain operational both during and after the overvoltage has occurred. power supply rails to guarantee correct operation of the device, 0.1 f decouplin g capacitors are required on the supply rails. . the adg5404f can operate with bipolar supplies between 5 v and 2 2 v. t he supplies on v dd and v ss do not need to be symmetrical , but the v dd to v ss range must not exceed 44 v. t h e adg5404f can also operate with single supplies between 8 v and 44 v , with v ss connected to gnd. the adg5404f is fully specified at the 15 v, 20 v, 12 v, a n d 36 v supply ranges. power supply sequenc ing protection the switch channel remains open when the device is unpowered , and signals from ?55 v to +55 v can be applied without damaging the device. only when the supplies are connected, a suitable digital control signal is placed on the a x pin s , and the signal is within normal operating range does the switch channel close. placing the adg5404f between external connectors and sensitive components offers protection in systems where a signal is presented to the source pins before the supply voltages are available. signal range the adg5404f has overvoltage detection circuitry on the inputs that compares the voltage levels at the source terminals with v dd and v ss . to protect downst ream circuitry from overvoltage conditions , supply the adg5404f with voltages that match the intended signal range. the low on - resistance switch allows signals up to the supply rails to be passed with very little distortion. a signal t hat exceeds the supply rail by the threshold voltage is then blocked. this signal block offers protection to both the device and any downstream circuitry. low impedance channe l protection the adg5404f can be used as a protective element in signal chains that are sensitive to both channel impedance and overvoltage signals. traditionally, series resistors limit the current during an overvoltage condition to protect susceptible components. these series resistors affect the performance of the signal chain and reduce the signal chain precision . a compromise must be reached on the value of the series resistance that is high enough to sufficiently protect sensitive components , but low enough that the precision performance of the signal chain is not sacrificed. the adg5404f enable s the designer to remove these resistors and retain precision performance without compromising the protection of the circuit. power supply recomme ndations analog devices, inc., has a wide range of power management products to meet the requirements of most high performance signal chains. an example of a bipolar power solution is shown in figure 52. the adp7118 and adp7182 can be used to generate clean positive and negative rails from the adp5070 dual switching regulator output. these rails can be used to power the adg5404f , the amplifier, and/or the precision converter in a typical signal chain. figure 52 . bipolar power solution table 10 . recommended power management devices product description adp5070 1 a/0.6 a, dc -to - dc switching regulator with independent positive and negative outputs adp7118 20 v, 200 ma, low noise, cmos ldo adp7142 40 v, 200 ma, low noise, cmos ldo adp7182 ? 28 v, ?200 ma, low noise, linear regulator high voltage surge suppression the adg5404f is not intended for use in very high voltage applications. the maximum operating voltage of the transistor is 80 v. in applications where the inputs are like ly to be s ubject to overvoltage conditions exceeding the breakdown voltage, use transient voltage suppressors (tvss) or similar devices . intelligent fault de tection the adg5404f digital output pin, ff, can interface with a microprocessor or control system and can be used as a n interrupt flag. this feature provides real - time diagnostic information on the state of the device and the system to which it connects. the control system can use the digital interrupt , ff , to start a variety of actions, as follows: ? i nitiating an investigation into the source of an overvoltage fault . ? shutting down critical systems in response to the overvoltage condition. ? using d ata recorders to mark data during these events as unreliable or out of specification . ldo +15v ?15v 12v input adp7182 ldo adp5070 adp7118 +16v ?16 v 12856-152
data sheet adg5404f rev. b | page 29 of 30 for systems sensitive during a start - up sequence, the active low operation of the flag allows the system to ensure that the adg5404f is powered on and tha t all input voltages are within the normal operating range before initiating operation. the ff pin is a weak pull - up, which allows the signals to combine into a single interrupt for larger modules that contain multiple devices. the recovery time, t digrec , can be decreased from a typical 60 s to 600 ns by using a 1 k? pull - up resistor. the specific fault digital output , sf can be used to decode which inputs are e xperiencing a fault condition. the sf pin reduces to below 0.8 v when a fault condition is detected on a specific pin, depending on the state o f f0 and f1 (see table 9 ). large voltage, high frequency signals figure 30 shows the voltage range and frequencies that the adg5404f can reliably convey . for signals extending across t he full signal range from v ss to v dd , keep the frequency below 3 mhz. if the required frequency is greater than 3 mhz, decrease the signal range appropriately to ensure signal integrity.
adg5404f data sheet rev. b | page 30 of 30 outline dimensions figure 53 . 1 4- lead thin shrink small outline package [tssop] (ru - 14 ) dimensions shown in millimet e r s figure 54 . 16 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 16 - 17) d imensions shown in millimeters ordering guide model 1 temperature range package description package option adg54 04 fbruz ? 40c to +125c 1 4 - lead thin shrink small outline package [tssop] r u -14 adg5404 fbruz -rl7 ? 40c to +125c 14 - lead thin shrink small outline package [tssop] ru -14 adg5404fbcpz -rl7 ? 40c to +125c 16 - lead lead frame chip scale package [lfcsp_wq] cp -16 -17 1 z = rohs compliant part. compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 se a ting plane 2.70 2.60 sq 2.50 compliant t o jedec standards mo-220-wggc. 1 0.65 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indica t or 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c ? 2014 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12856 - 0- 1/16(b)

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